1. Field of the Invention
The present invention relates to a source driver, and more particularly, to a source driver with high driving ability, high stability and high charge-sharing efficiency.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a source driver according to the prior art. The source driver 10 comprises a gamma resistor voltage divider 11, a first digital-to-analog converter (DAC) 12, a second DAC 13, a first operational amplifier 14, a second operational amplifier 16, a first output switch 18, a second output switch 20, a first resistor 22, a second resistor 24 and a charge-sharing switch 26. The first output switch 18 and the second output switch 20 are transmission gates respectively controlled by a set of control signals OPC, OPCB, and the charge-sharing switch 26 is controlled by a control signal EQC. The first resistor 22 and the second resistor 24 are electrostatic discharge (ESD) protection resistors, and the resistance of each of the ESD resistors is R.
In General, in order to increase the driving ability of the source driver 10, increasing areas of the first output switch 18 and the second output switch 20 (this means to reduce the equivalent resistances of the output switches 18, 20) or reducing the resistances of the first resistor 22 and the second resistor 24 should be done so as to reduce the resistance between an output current path of the first operational amplifier 14 and the second operational amplifier 16 to a load.
But the resistance also provides a zero point for a system, which is beneficial to the stability of the system. Therefore, it improves the stability of the system to reduce the areas of the first output switch 18 and the second output switch 20 (this means to increase the equivalent resistances of the output switches 18, 20) or increase the resistances of the first resistor 22 and the second resistor 24.
Please refer to both FIG. 1 and FIG. 2. FIG. 2 is an operational waveform diagram of the source driver shown in FIG. 1. Because the liquid crystal cannot stay in a fixed electric potential too long, the liquid crystal requires reversing. In addition, one of a first output channel AVO_ODD and a second output channel AVO_EVEN of the source driver 10 must be a positive electric potential, and the other must be a negative electric potential. Therefore, the source driver 10 often performs the charge sharing through the charge-sharing switch 26 after an operation of driving loads so as to save electrical powers.
As shown in FIG. 2, when the control signal OPC is changed from a high level to a low level, the first output switch 18 and the second output switch 20 are turned off, so the resistance of the source driver 10 for the load end is high. At this time, the gamma resistor voltage divider 11 transmits data of a desired level respectively to the first DAC 12 and the second DAC 13.
Next, when the control signal EQC is changed to the high level, the charge-sharing switch 26 is turned on, and the system enters into the charge-sharing timing t2. At this time, the electric charges at the load end are redistributed through the charge-sharing switch 26, so that the electric potential of the first output channel AVO_ODD and the second output channel AVO_EVEN of the source driver 10 can reach an intermediate value.
Then, the control signal EQC is changed from the high level to the low level, and the charge-sharing switch 26 is turned off. Therefore, the charge-sharing timing t2 ends. At this time, the control signal OPC is also changed from the low level to the high level, and the first output switch 18 and the second output switch 20 are therefore turned on so as to make the system enter an output timing t1. Assume the first output channel AVO_ODD of the source driver 10 is required to reach a negative electric potential, and the second output channel AVO_EVEN is required to reach a positive electric potential, a buffer made up of the first DAC 12 through the first operational amplifier 14 outputs the negative electric potential to the first output channel AVO_ODD, and a buffer made up of the second DAC 13 through the second operational amplifier 16 outputs the positive electric potential to the second output channel AVO_EVEN.
Please note that the resistances of the first resistor 22 and the second resistor 24 affect the efficiency of charge sharing during the charge-sharing timing t2. When the resistances of the first resistor 22 and the second resistor 24 are larger, the time taken by the electric potential of the first output channel AVO_ODD and the second output channel AVO_EVEN of the source driver 10 to reach the intermediate value is longer (it means the time spent for charge-sharing is getting longer), so the efficiency of the charge sharing is lower. During the output timing t1, the resistances of the first resistor 22 and the second resistor 22 limit the driving ability of the source driver 10. In addition, when the resistances of the first resistor 22 and the second resistor 24 are larger, the time taken by the electric potential of the first output channel AVO_ODD and the second output channel AVO_EVEN of the source driver 10 to reach the final value is longer. However, assume the resistances of the equivalent resistor of the output switch and the ESD protection resistor are reduced, the driving ability and the efficiency of the charge sharing of the source driver can be improved, but the stability of the system also becomes worse.